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XR-2212
...the analog plus company TM
Precision Phase-Locked Loop
October 2006
FEATURES D Quadrature VCO Outputs D Wide Frequency Range (0.01Hz to 300kHz) D Wide Supply Voltage Range (4.5V to 20V) D TTL/HCMOS Compatible (VCC = 5VDC) D Wide Dynamic Range (2mV to 3Vrms) D Adjustable Tracking Range ("1% to "80%) D Excellent Temp. Stability 20ppm/C, Typ. GENERAL DESCRIPTION The XR-2212 is an ultra-stable monolithic phase-locked loop (PLL) system especially designed for data communications and control system applications. Its on board reference and uncommitted operational amplifier, together with a typical temperature stability of better than 20ppm/C, make it ideally suited for frequency synthesis, ORDERING INFORMATION
Part No. XR-2212M XR-2212CP
APPLICATIONS D Frequency Synthesis D Data Synchronization D FM Detection D Tracking Filters D FSK Demodulation
FM detection, and tracking filter applications. The wide input dynamic range, large operating voltage range, large frequency range, and HCMOS and TTL compatibility contribute to the usefulness and wide applicability of this device.
Package 16 Lead 300 Mil CDIP 16 Lead 300 Mil PDIP
Operating Temperature Range -55C to +125C 0C to +70C
BLOCK DIAGRAM
VCC Pre Amplifier INP 2 Phase Detector 1 GND 4
10 15
0-DET O VCOQO VCOOC VCOOV VREF
0-DET I 16 TIM C1 14 VCO TIM C2 13 TIM R 12 PINP NINP 9 Op Amp 7 8 6 OUT COMP VREF Amp 3 5 11
Figure 1. XR-2212 Block Diagram
Rev. 2.10
E1979-2006
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1
XR-2212
PIN CONFIGURATION
VCC INP VCOOC GND VCOOV COMP NINP OUT
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
0-DET I VCOQO TIM C1 TIM C2 TIM R VREF 0-DET O PINP
16 Lead PDIP, CDIP (0.300")
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VCC INP VCOOC GND VCOOV COMP NINP OUT PINP 0-DET O VREF TIM R TIM C2 TIM C1 VCOQO 0-DET I O I I O I O O I I I O I I O Type Description Positive Power Supply. Receive Analog Input. VCO Current Output. Ground Pin. VCO Voltage Source Output. Uncommitted Amplifier, Frequency Compensation Input. Inverted Input. Uncommitted amplifier. Uncommitted Amplifier Output. Positive Input. Uncommitted amplifier. Phase Detector Output. Internal Voltage Reference. The value of VREF is VCC /2 -650mV. Timing Resistor Input. This pin connects to the timing resistor of the VCO. Timing Capacitor Input. The timing capacitor connects between this pin and pin 14. Timing Capacitor Input. The timing capacitor connects between this pin and pin 13. VCO Quadrature Output. Phase Detector Input.
Rev. 2.10 2
XR-2212
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = +12V, TA = + 25C, R0 = 30kW, C0 = 0.033mF, unless otherwise specified. See Figure 3 for component designation.
XR-2212M Parameter P t General Characteristics Supply Voltage Supply Current Oscillator Section Frequency Accuracy Frequency Stability Temperature Power Supply Upper Frequency Limit Lowest Practical Operating Frequency F Timing Resistor, R0 Operating Range Recommended Range Oscillator Outputs Voltage Output Positive Swing, VOH Negative Swing, VOL Current Sink Capability Current Output Peak Current Swing Output Impedance Quadrature Output Output Swing DC Level Output Impedance Loop Phase Detector Section Peak Output Current Output Offset Current Output Impedance Maximum Swing +4 +150 +200 +1 1 +5 +4 +300 +100 +200 +2 1 +5 +300 mA mA MW V Referenced to Pin 11 0.6 0.3 3 0.6 0.3 3 V V kW Measured at Pin 10 Referenced to Pin 11 100 150 1 150 1 mA MW Measured at Pin 15 11 0.4 1 0.8 11 0.5 1 V V mA Measured at Pin 3 Measured at Pin 5 5 15 2000 100 5 15 2000 100 kW kW See Figure 8 and Figure 9 100 +20 0.05 0.2 300 0.01 +50 0.5 +20 0.05 0.2 300 0.01 ppm/C %/V %/V kHz Hz +1 +3 +1 % Deviation from f0 = 1/R0C0 R1 = R See Figure 9 VCC = 12 + 1V, See Figure 8 VCC = 5 + 0.5V, See Figure 8 R0 = 8.2kW, C0 = 400pF R0 = 2MW, C0 = 50mF See Figure 5 4.5 6 15 10 4.5 6 15 12 V mA R0 > 10kW., See Figure 5 Min. Typ. Max. Min. XR-2212CP Typ. Max. Units U it Conditions C diti
Note Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 2.10 3
XR-2212
ELECTRICAL CHARACTERISTICS (CONT'D)
XR-2212M Parameter Input Preamp Section Input Impedance Input Signal to Cause Limiting Op Amp Section Voltage Gain Input Bias Current Offset Voltage Slew Rate Internal Reference Voltage Level Output Impedance Maximum Source Current 4.9 5.3 100 80 5.7 4.75 5.3 100 80 5.85 V W WA AC Small Signal 55 70 0.1 +5 2 1 +20 55 70 0.1 +5 2 1 +20 dB mA mV V/msec Measured at Pin 11 RL = 5.1kW, RF = R 20 2 10 20 2 kW mV rms Min. Typ. Max. Min. XR-2212CP Typ. Max. Units Conditions Measured at Pin 2
Note Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms Power Dissipation: Ceramic Package: . . . . . . . . . . . . . . . . . . . . . . . Derate Above TA = + 25C . . . . . . . . Plastic Package: . . . . . . . . . . . . . . . . . . . . . . . . Derate Above TA = + 25C . . . . . . . . 750mW 6mW/C 625mW 5mW/C
SYSTEM DESCRIPTION The XR-2212 is a complete PLL system with buffered inputs and outputs, an internal reference, and an uncommitted op amp. Two VCO outputs are pinned out; one sources current, the other sources voltage. This enables operation as a frequency synthesizer using an external programmable divider. The op amp section can be used as an audio preamplifier for FM detection or as a high speed sense amplifier (comparator) for FSK demodulation. The center frequency, bandwidth, and tracking range of the PLL are controlled independently by
Rev. 2.10 4
external components. The PLL output is directly compatible with CMOS, HCMOS and TTL logic families as well as microprocessor peripheral systems. The precision PLL system operates over a supply voltage range of 4.5V to 20V, a frequency range of 0.01Hz to 300kHz, and accepts input signals in the range of 2mV to 3V rms. Temperature stability of the VCO is typically better than 20 ppm/C with the optimum timing resistor value.
XR-2212
Pre Amp Signal Input Phase Detector
Loop Filter + Op Amp
0-DET Input
VCO Voltage Output VCO Current Output
AMP VCO Phase Quadrature Output
Figure 2. Functional Block Diagram of XR-2212 Precision PLL System
VCC 6 2 0.1mF 16 0.1mF R3 0.1mF 5 %N External Divider (Optional) 14 VCO 13 CO R0 12 R1 Phase Detector 10 C1 RC 9 8 RF CO Demod Output RL 5.6K
Input Signal
Figure 3. Generalized Circuit Connection for FM Detection, Signal Tracking or Frequency Synthesis
Rev. 2.10 5
AA AA
11
7
Internal Reference
XR-2212
Phase Detector Input
1 Loop Phase Detector Output 10 11 Vcc Reference Output Voltage
16 Signal Input 2 30K 30K
Input Preamplifier
Phase Detector
Internal Voltage Reference
2K
2K Timing Capacitor C0 13 14 A VCO Quad Out 15 A1 3 5K A1
VCO Current Output
VCO Out 5 Inv Inp 7
Non Inv Inp 9
Amp Out 8
5K
A
6 Comp
5K 12 Timing Resistor
5K Op Amp RO 4 GND
Figure 4. Simplified Circuit Schematic of XR-2212
Rev. 2.10 6
XR-2212
TYPICAL CHARACTERISTICS
20
10 R0=5kW
Supply Current (mA)
15 RL = 5K C 0 ( mF ) RL = 10K 10 RL > 100K
R0=10kW
0.1
R0=20kW R0=40kW
5 R0=80kW 0 4 6 8 10 12 14 16 18 20 22 24 Supply Voltage VCC (V) 0.01 100 R0=160kW 1000 f0 (Hz) 10,000
Figure 5. Typical Supply Current vs. VCC (Logic Outputs Open Circuited)
Figure 6. VCO Frequency vs. Timing Resistor
1000 C0=0.001mF Normalized Frequency 1.02 5 1.01 1.00 3 0.99 0.98 2
CURVE 1 2 3 4 5
f0 = 1kHz R > 10R0 2 1 4
5
C0=0.0033mF R0 (k W ) C0=0.01mF 100 C0=0.033mF
3 4
R0 5K 10K 30K 100K 300K
C0=0.1mF C0=0.33mF 10 0 1000 f0 (Hz) 10,000
1 0.97 4 6 8 10 12 14 VCC (V) 16
18
20
22
24
Figure 7. VCO Frequency vs. Timing Capacitor
Figure 8. Typical f0 vs. Power Supply Characteristics
Rev. 2.10 7
XR-2212
Normalized Frequency Drift (% of f o ) +1.0 R0=10K +0.5 500K R0=50K 0 R0=500K -0.5 R0=1M -1.0 -50 VCC=12V R1=12R0 f0=1kHz 0 25 50 75 100 50K 10K 1M
-25
125
Temperature (C)
Figure 9. Typical Center Frequency Drift vs. Temperature
DESCRIPTION OF CIRCUIT CONTROLS Signal Input (Pin 2): Signal is AC coupled to this terminal. The internal impedance at Pin 2 is 20kW. Recommended input signal level is in the range of 10mV to 5V peak-to-peak. VCO Current Output (Pin 3): This is a high impedance (MW) current output terminal which can provide +100mA drive capability with a voltage swing equal to VCC. This output can directly interface with CMOS or NMOS logic families. VCO Voltage Output (Pin 5): This terminal provides a low- impedance ( 50W) buffered output for the VCO. It can directly interface with low-power Schottley TTL. For interfacing with standard TTL circuits, a 750W pull-down resistor from Pin 5 to ground is required. For operation of the PLL without an external divider, Pin 5 can be DC coupled to Pin 16. Op Amp Compensation (Pin 6): The op amp section is frequency compensated by connecting an external capacitor from Pin 6 to the amplifier output (Pin 8). For unity-gain compensation a 20pF capacitor is recommended. Op Amp Inputs (Pins 7 and 9): These are the inverting and the non-inverting inputs for the op amp section. The common-mode range of the op amp inputs is from +1V to (VCC - 1.5) volts.
Rev. 2.10 8
Op Amp Output (Pin 8): The op amp output is an opencollector type gain stage and requires a pull-up resistor, RL, to VCC for proper operation. For most applications, the recommended value of RL is in 5kW to 10kW range. Phase Detector Output (Pin 10): This terminal provides a high-impedance output for the loop phase-detector. The PLL loop filter is formed by R1 and C1 connected to Pin 10 (see Figure 3). With no input signal, or with no phase-error within the PLL, the DC level at Pin 10 is very nearly equal to VREF. The peak voltage swing available at the phase detector output is equal to $VREF. Reference Voltage, VREF (Pin 11): This pin is internally biased at the reference voltage level. VREF:VREF = VCC/2 - 650mV. The DC voltage level at this pin forms an internal reference for the voltage levels at Pins 10, 12 and 16. Pin 1 must be bypassed to ground with a 0.1mF capacitor, for proper operation of the circuit. VCO Control Input (Pin 12): VCO free-running frequencies determined by external timing resistor, R0, connected from this terminal to ground. For optimum temperature stability, R0 must be in the range of 10KW to 100kW (see Figure 9). VCO Frequency Adjustment: VCO can be fine-tuned by connecting a potentiometer, RX, in series with R0 at Pin 12 (see Figure 11). This terminal is a low-impedance point, and is internally biased at a DC level equal to VREF. The maximum timing
XR-2212
current drawn from Pin 12 must be limited to <3 mA for proper operation of the circuit. VCO Timing Capacitor (Pins 13 and 14): VCO frequency is inversely proportional to the external timing capacitor, C0, connected across these terminals (see Figure 6). C0 must be nonpolar, and in the range of 200pF to 10mF. VCO Quadrature Output (Pin 15): The low-level ([ 0.6Vpp) output at this pin is at quadrature phase (i.e. 90 phase-offset) with the other VCO outputs at Pins 3 and 5. The DC level at Pin 15 is approximately 300mV above VREF. The quadrature output can be used with an external multiplier as a "lock detect" circuit. In order not to degrade oscillator performance, the output at Pin 15 must be buffered with an external high impedance low capacitance amplifier. When not in use, Pin 15 should be left open-circuited. Phase Detector Input (Pin 16): Voltage output of the VCO (Pin 5) or the output of an external frequency divider is connected to this pin. The DC level of the sensing threshold for the phase detector is referenced to VREF. If the signal is capacitively coupled to Pin 16, then this pin must be biased from Pin 11, through an external resistor, RB (RB [ 10kW). The peak voltage swing applied to Pin 16 must not exceed (VCC - 1.5) volts. PHASE-LOCKED LOOP PARAMETERS Transfer Characteristics
Figure 10 shows the basic frequency to voltage characteristics of XR-2212. With no input signal present, filtered phase detector output voltage is approximately equal to the internal reference voltage, VREF at Pin 11. The PLL can track an input signal over its tracking bandwidth, shown in the figure. The frequencies fTL and fTH represent the lower and the upper edge of the tracking range, f0 represents the VCO center frequency.
Tracking Bandwidth Df Df
2VR Phase Detector Output (Pin 10)
VR
0 fTL fO fTH Frequency
Input Signal Frequency
Figure 10. Phase Detector Output Voltage (Pin 10) as a Function of Input Signal Frequency
Note Output Voltage is Referenced to Internal Reference Voltage VREF at Pin 11
Rev. 2.10 9
XR-2212
Design Equations (See Figure 3 and Figure 10 for definition of components.) 1. VCO Center Frequency, f0: f0 = 1/R0C0 Hz 2. Internal Reference Voltage, VREF (measured at Pin 11) VREF = VCC/2 - 650mV 3. Loop Low-Pass Filter Time Constant, t : t = R1C1 4. Loop Damping, j: j + 0.25 8. Total Loop Gain, KT KT = 2pKO K0 = 4/C0R1 rad/sec/volt 9. Peak Phase-Detector Current, IA; available at Pin 10. IA = VREF (volts)/25mA APPLICATION INFORMATION
FM Demodulation XR-2212 can be used as a linear FM demodulator for both narrow-band and wide-band FM signals. The generalized circuit connection for this application is shown in Figure 11, where the VCO output (Pin 5) is directly connected to the phase detector input (Pin 16). The demodulated signal is obtained at phase detector output (Pin 10). In the circuit connection of Figure 10, the op amp section of XR-2212 is used as a buffer amplifier to provide both additional voltage amplification as well as current drive capability. Thus, the demodulated output signal available at the op amp output (Pin 8) is fully buffered from the rest of the circuit. In the circuit of Figure 11, R0C0 set the VCO center frequency, R1 sets the tracking bandwidth, C1 sets the low-pass filter time constant. Op amp feedback resistors RF and RC set the voltage gain of the amplifier section.
NC 0 C1
where N is the external frequency divider modular (See 2). If no divider is used, N = 1. 5. Loop Tracking Bandwidth, $Df/f0: Df/f0 = R0/R1 6. Phase Detector Conversion Gain, KO: (KO is the differential DC voltage across Pins 10 and 11, per unit of phase error at phase-detector input) KO = -2VREF/p volts/radian 7. VCO Conversion Gain, K0: (K0 is the amount of change in VCO frequency, per unit of DC voltage change at Pin 10. It is the reciprocal of the slope of conversion characteristics shown in Figure 10). K0 = -1/VREFC0R1 Hz/V
Rev. 2.10 10
XR-2212
VCC
1 2 0.1mF FM Input 4 Phase Detector 10 C1
VCC 9 7 RF
6 8
0.1mF 30pF RL 5K Demod Output
16 RC 11 Internal Reference
0.1mF 5 VCO 14 13 CO Rx Fine Tune R0 R1 12
Figure 11. Circuit Connection for FM Demodulation
Design Instructions The circuit of Figure 11 can be tailored to any FM demodulation application by a choice of the external components R0, R1, RC, RF, C0 and C1. For a given FM center frequency and frequency deviation, the choice of these components can be calculated as follows, using the design equations and definitions given on page 10. a) Choose VCO center frequency f0 to be the same as FM carrier frequency. b) Choose value of timing resistor R0, to be in the range of 10kW to 100kW. This choice is arbitrary. The recommended value is R0 + 20kW. The final value of R0 is normally fine-tuned with the series potentiometer, RX. c) Calculate value of C0 from design equation (1) or from Figure 7: C0 = 1/R0f0
Rev. 2.10 11
d) Choose R1 to determine the tracking bandwidth, Df (see design equation 5). The tracking bandwidth, Df, should be set significantly wider than the maximum input FM signal deviation, DfSM. Assuming the tracking bandwidth to be "N" times larger than DfSM, one can re-unite design equation 5 as: Df + R 0 + N Df SM R1 f0 f0
Table 2. lists recommended values of N, for various values of the maximum deviation of the input FM signal.
e) Calculate C1 to set loop damping (see design equation 4). Normally, = 1/2 is recommended. Then, C1 = C0/4 for = 1/2.
XR-2212
% Deviation of FM Signal (DfSM/f0) 1% or less 1% to 3% 1% to 5% 5% to 10% 10% to 30% 30% to 50% Recommended Value of Bandwidth Ratio, N (N = Df/DfSM) 10 5 4 3 2 1.5
R0 /R1 = (3)(0.0746) = 0.224 or: R1 = 89.3kW.
Step e): Calculate C1 = (C0 /4) = 186pF. Step f): Calculate RC and RF to get $4V peak output swing: Let RF = 100kW. Then,
RC = 80.6kW.
Note: All values except R0 can be rounded-off to nearest standard value.
Table 2. Recommended values of bandwidth ratio, N, for various values of FM signal frequency deviation. (Note: N is the ratio of tracking bandwidth Df to max. signal frequency deviation, DfSM). f) Calculate RC and RF to set peak output signal amplitude. Output signal amplitude, VOUT, is given as:
FREQUENCY SYNTHESIS
Figure 12 shows the generalized circuit connection for frequency synthesis. In this application an external frequency divider is connected between the VCO output (Pin 5) and the phase-detector input (Pin 16). When the circuit is in lock, the two signals going into the phase-detector are at the same frequency, or fS = f1/N where N is the modulus of the external frequency divider. Conversely, the VCO output frequency, f1 is equal to NfS.
In the circuit configuration of Figure 12, the external timing components, R0 and C0, set the VCO free running frequency; R1 sets the tracking bandwidth and C1 sets the loop damping, i.e., the low-pass filter time constant (see design equations). The total tracking range of the PLL (see Figure 10), should be chosen to accommodate the lowest and the highest frequency, fmax and fmin, to be synthesized. A recommended choice for most applications is to choose a tracking half-bandwidth Df, such that: Df fmax - fmin If a variable input frequency and a variable counter modulus N is used, then the maximum and the minimum values of output frequency will be:
VOUT + DfSM (VREF) R1 R0 f0
RC ) RF RC
In most applications, RF = 100kW is recommended; then RC, can be calculated from the above equation to give desired output swing. The output amplifier can also be used as a unity-gain voltage follower, by open circuiting RC (i.e., RC = ).
Note: All calculated component values except R0 can be rounded-off to the nearest standard value, and R0 can be varied to fine-tune center frequency, through a series potentiometer, RX , (See Figure 11).
Design Example Demodulator for FM signal with 67kHz carrier frequency with $5kHz frequency deviation. Supply voltage is +12V and required peak output swing is $4V. Step a) Step b) Step c) Step d) f0 is chosen as 67kHz. Choose R0 = 20kW (18kW fixed resistor in series with 5kW potentiometer). Calculate C0; from design equation (1).
fmax = Nmax (fS )max and fmin = Nmin (fS )min
If a fixed output frequency is desired, i.e. N and fS are fixed, then a $10% tracking bandwidth is recommended. Excessively large tracking bandwidth may cause the PLL to lock on the harmonics of the input signals; and the small tracking range increases the "lock-up" or acquisition time. Design Instructions For a given performance requirement, the circuit of Figure 12 can be optimized as follows: a) Choose center frequency, f0, to be equal to the output frequency to be synthesized. If a range of output
C0 = 746pF
Calculate R1. For given FM deviation, DfSM/f0 = 0.0746, and N = 3 from Table 2. Then:
Rev. 2.10 12
XR-2212
frequencies is desired, set f0 to be at mid-point of the desired range. b) Choose timing resistor R0 to be in the range of 15kW to 100kW. This choice is arbitrary. R0 can be fine tuned with a series potentiometer, RX. c) Choose timing capacitor, C0 from Figure 7 or Equation 1. d) Calculate R1 to set tracking bandwidth (see Figure 10 and design equation 5). If a range of output frequencies are desired, set R1 to get: Df = fmax - fmin If a single fixed output frequency is desired, set R1 to get: Df = 0.1 f0 e) Calculate C1 to obtain desired loop damping. (See design equation 4). For most applications, = 1/2 is recommended, thus:
C0 = NC0 /4
Note All component values except R0 can be rounded off to the nearest standard value.
VCC
0.1mF 1 2 0.1mF 4 Phase Detector 10 C1 16 74LS90 or Similar 0.1mF 12 VCO F1 = Nfs 1K 14 13 CO R0 R1 11 Internal Reference VCC 9 7 6 8
Input Signal
%N FO= F1/N Output 5
Figure 12. Circuit Connection for Frequency Synthesizer
Rev. 2.10 13
XR-2212
INPUT SENSITIVITY The input to the XR-2212 may sometimes be too sensitive to noise conditions on the input line. Figure 13 illustrates a method of de-sensitizing the XR-2212 from such noisy line conditions by the use of a resistor, Rx, connected from pin 2 to ground. The value of Rx is chosen by the equation and the desired minimum signal threshold level. VIN minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold).
V IN minimum (peak) + V a-V b +
DV " 2.8V offset + VREF + 20, 000 or (20, 000 ) RX)
RX + 20, 000 VREF * 1 DV
Vcc
To Phase Detector Input Va Vb
Rx
VREF 11
Figure 13. Desensitizing Input Stage
Rev. 2.10 14
II
2
20K
20K
II II
XR-2212
16 LEAD CERAMIC DUAL-IN-LINE (300 MIL CDIP)
Rev. 1.00
16 1
9 8
E D Base Plane Seating Plane L e B B1 c A1 A E1
INCHES SYMBOL A A1 B B1 c D E1 E e L MIN 0.100 0.015 0.014 0.045 0.008 0.740 0.250 MAX 0.200 0.060 0.026 0.065 0.018 0.840 0.310
MILLIMETERS MIN 2.54 0.38 0.36 1.14 0.20 18.80 6.35 MAX 5.08 1.52 0.66 1.65 0.46 21.34 7.87
0.300 BSC 0.100 BSC 0.125 0 0.200 15
7.62 BSC 2.54 BSC 3.18 0 5.08 15
Note: The control dimension is the inch column
Rev. 2.10 15
XR-2212
16 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
Rev. 1.00
16 1 D
9 8 E1 E A2
Seating Plane
A L A1 B e B1
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.745 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 0.840 0.325 0.280
MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 18.92 7.62 6.10 MAX 5.33 1.78 4.95 0.56 1.78 0.38 21.34 8.26 7.11
0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15
2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 4.06 15
Note: The control dimension is the inch column
Rev. 2.10 16
XR-2212 Notes
Rev. 2.10 17
XR-2212 Notes
Rev. 2.10 18
XR-2212 Notes
Rev. 2.10 19
XR-2212
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1979-2006 EXAR Corporation Datasheet October 2006 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.10 20

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